Semiconductor devices have realized improvements in performance such as high speed, sophisticated functions, low power dissipation, and low cost by continuing remarkable miniaturization and high integration according to Moore's Law. However, with further miniaturization such as 90 nm and 65 nm, because of financial problems such as the increase of capital investment and research and development costs, and technical problems such as increase of idle current of transistors, promotion of miniaturization according to conventional development speed has become difficult. Against these problems, development of a lamination System-in-Package (SiP), which three-dimensionally combines multiple LSIs, is considered to be a promising solution. This is because the lamination SiP is a high-density packaging and thus can be a means of realizing a function exceeding System-On-Chip (SoC) by optimal system design. There are three methods for the 3D lamination structure process: Chip-to-Chip process, Chip-to-Wafer process, and Wafer-to-Wafer process.